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hot swap controller and digital power and energy monitoring with pmbus interface adm1276 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features controls supply voltages from 2 v to 20 v 370 ns response time to short circuit resistor-programmable 5 mv to 25 mv current limit 1% accurate, 12-bit adc for current, v in /v out readback charge pumped gate drive for multiple external n-channel fets high gate drive voltage to ensure lowest r dson foldback for tighter fet soa protection automatic retry or latch-off on current fault programmable current-limit timer for soa programmable, multifunction gpo power-good status output analog uv and ov protection enable pin peak detect registers for current and voltage pmbus fast mode compliant interface 20-lead lfcsp applications power monitoring and control/power budgeting central office equipment telecommunication and data communication equipment pcs/servers functional block diagram 09718-001 gate sense+ timer timer adm1276-3 gnd sense? vcc v cp vcap enable iout uv ov 1.0v 1.0v vout vout 12-bit adc scl sda adr sense+ iout ldo charge pump timeout gpo2/alert2 pwrgd latch timer on ss current limit flb iset timeout current limit control ref select 1.0v gate drive/ logic logic and pmbus 50 + + + + ? ? ? ? figure 1. general description the adm1276 is a hot swap controller that allows a circuit board to be removed from or inserted into a live backplane. it also features current and voltage readback via an integrated 12-bit analog-to- digital converter (adc), accessed using a pmbus? interface. the load current is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the sense+ and sense? pins. a default limit of 20 mv is set, but this limit can be adjusted, if required, using a resistor divider network from the internal reference voltage to the iset pin. the adm1276 limits the current through the sense resistor by controlling the gate voltage of an external n-channel fet in the power path, via the gate pin. the sense voltageand, therefore, the load currentis maintained below the preset maximum. the adm1276 protects the external fet by limiting the time that the fet remains on while the current is at its maximum value. this current-limit time is set by the choice of capacitor connected to the timer pin. in addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the fet is increased. this helps to maintain constant power in the fet and allows the safe operating area (soa) to be adhered to in an effective manner. in case of a short-circuit event, a fast internal overcurrent detector responds within 370 ns and signals the gate to shut down. a 1500 ma pull-down device ensures a fast fet response. the adm1276 features overvoltage (ov) and undervoltage (uv) protection, programmed using external resistor dividers on the uv and ov pins. a pwrgd signal can be used to detect when the output supply is valid, using the flb pin to monitor the output. a gpo pin can be configured as an output signal that can be asserted when a programmed current or voltage level is reached. the 12-bit adc can measure the current in the sense resistor, as well as the supply voltage on the sense+ pin or the output voltage. a pmbus interface allows a controller to read current and voltage data from the adc. measurements can be initiated by a pmbus command. alternatively, the adc can run conti- nuously, and the user can read the latest conversion data whenever required. as many as four unique pmbus addresses can be selected, depending on the way that the adr pin is connected. the adm1276 is available in a 20-lead lfcsp and has a latch pin that can be configured for automatic retry or latch-off when an overcurrent fault occurs.
adm1276 rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications..................................................................................... 4 serial bus timing characteristics .............................................. 7 absolute maximum ratings............................................................ 8 thermal characteristics .............................................................. 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 11 typical application circuit ........................................................... 17 theory of operation ...................................................................... 18 powering the adm1276............................................................ 18 current sense inputs.................................................................. 18 current-limit reference ........................................................... 19 setting the current limit (iset) ............................................. 19 soft start ...................................................................................... 20 foldback....................................................................................... 20 timer............................................................................................ 21 hot swap retry duty cycle ...................................................... 21 fet gate drive clamps............................................................. 21 fast response to severe overcurrent ...................................... 22 undervoltage and overvoltage................................................. 22 enable input ............................................................................ 22 power good................................................................................. 22 vout measurement ................................................................. 23 fet health .................................................................................. 23 power monitor ............................................................................ 23 pmbus interface ............................................................................. 24 device addressing...................................................................... 24 smbus protocol usage............................................................... 24 packet error checking............................................................... 24 smbus message formats ........................................................... 25 group commands...................................................................... 26 hot swap control commands ................................................. 27 adm1276 information commands ........................................ 27 status commands....................................................................... 27 gpo and alert pin setup commands..................................... 28 power monitor commands ...................................................... 28 warning limit setup commands ............................................ 29 pmbus direct format conversion .......................................... 30 voltage and current conversion using lsb values.............. 32 gpo2/ alert2 pin behavior ....................................................... 33 faults and warnings .................................................................. 33 generating an alert ................................................................... 33 handling/clearing an alert ...................................................... 33 smbus alert response address ............................................... 33 example use of smbus alert response address ................... 34 pmbus command reference........................................................ 35 operation .............................................................................. 36 clear_faults........................................................................ 36 capability.............................................................................. 36 vout_ov_warn_limit..................................................... 36 vout_uv_warn_limit..................................................... 36 iout_oc_warn_limit ...................................................... 36 iout_warn2_limit............................................................. 36 vin_ov_warn_limit ......................................................... 37 vin_uv_warn_limit ......................................................... 37 pin_op_warn_limit .......................................................... 37 status_byte .......................................................................... 37 status_word........................................................................ 38 status_vout ......................................................................... 38 status_iout .......................................................................... 38 status_input........................................................................ 39 status_mfr_specific........................................................ 39 read_ein.................................................................................. 40 read_vin ................................................................................. 40 read_vout............................................................................. 40 read_iout .............................................................................. 40 read_pin.................................................................................. 40 pmbus_revision .................................................................. 40 mfr_id....................................................................................... 41 mfr_model ............................................................................ 41 mfr_revision........................................................................ 41 peak_iout............................................................................... 41 peak_vin.................................................................................. 41 peak_vout ............................................................................. 42 pmon_control ................................................................... 42
adm1276 rev. 0 | page 3 of 48 pmon_config........................................................................42 alert2_config .....................................................................43 device_config .....................................................................44 power_cycle.........................................................................44 peak_pin ...................................................................................44 read_pin_ext ........................................................................44 read_ein_ext........................................................................44 outline dimensions........................................................................45 ordering guide ...........................................................................45 revision history 3/11revision 0: initial version
adm1276 rev. 0 | page 4 of 48 specifications v cc = 2.95 v to 20 v, v cc v sense+ , v sense+ = 2 v to 20 v, v sense = (v sense+ ? v sense? ) = 0 v, t a = ?40c to +85c, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions/comments power supply operating voltage range v cc 2.95 20 v undervoltage lockout 2.4 2.7 v v cc rising undervoltage hysteresis 90 120 mv quiescent current i cc 5 ma gate on and power monitor running uv pin input current i uv 100 na uv 3.6 v uv threshold uv th 0.97 1.0 1.03 v uv falling uv threshold hysteresis uv hyst 40 50 60 mv uv glitch filter uv gf 2 7 s 50 mv overdrive uv propagation delay uv pd 5 8 s uv low to gate pull-down active ov pin input current i ov 100 na ov 3.6 v ov threshold ov th 0.97 1.0 1.03 v ov rising ov threshold hysteresis ov hyst 50 60 70 mv ov glitch filter ov gf 0.5 1.5 s 50 mv overdrive ov propagation delay ov pd 1.0 2 s ov high to gate pull-down active sense+ and sense? pins input current i sensex 150 a per individual pin; sense+, sense? = 20 v input imbalance i sense 5 a i sense = (i sense+ ) ? (i sense? ) vcap pin internally regulated voltage v vcap 2.66 2.7 2.74 v 0 a i vcap 100 a; c vcap = 1 f iset pin reference select threshold v isetrsth 1.35 1.5 1.65 v if v iset > v isetrsth , an internal 1 v reference (v clref ) is used internal reference v clref 1 v accuracies included in total sense voltage accuracies gain of current sense amplifier av csamp 50 v/v accuracies included in total sense voltage accuracies input current i iset 100 na v iset v vcap gate pin maximum voltage on the gate is always clamped to 31 v gate drive voltage v gate v gate = v gate ? v sense+ 10 12 14 v 17 v v cc 8 v; i gate 5 a 4.5 13 v 20 v v cc 17 v; i gate 5 a 8 10 v v sense+ = v cc = 5 v; i gate 5 a 4.5 6 v v sense+ = v cc = 2.95 v; i gate 1 a gate pull-up current i gateup ?20 ?30 a v gate = 0 v gate pull-down current i gatedn regulation i gatedn_reg 45 60 75 a v gate 2 v; v iset = 1.0 v; (sense+) ? (sense?) = 30 mv slow i gatedn_slow 5 10 15 ma v gate 2 v fast i gatedn_fast 750 1500 2000 ma v gate 12 v; v cc 12 v gate holdoff resistance 20 v cc = 0 v hot swap sense voltage hot swap sense voltage current limit v sensecl 19.6 20 20.4 mv v iset > 1.65 v; v flb > 1.12 v; v gate = (sense+) + 3 v; i gate = 0 a; v ss 2 v foldback inactive v gate = (sense+) + 3 v; i gate = 0 a; v ss 2 v 24.6 25 25.4 mv v iset = 1.25 v; v flb > 1.395 v 19.6 20 20.4 mv v iset = 1.0 v; v flb > 1.12 v 9.6 10 10.4 mv v iset = 0.5 v; v flb > 0.57 v 4.6 5 5.4 mv v iset = 0.25 v; v flb > 0.295 v
adm1276 rev. 0 | page 5 of 48 parameter symbol min typ max unit test conditions/comments foldback active 3.5 4 4.5 mv v flb = 0 v; v gate = (sense+) + 3 v; i gate = 0 a; v ss 1 v 9.6 10 10.4 mv v iset > 1.0 v; v flb = 0.5 v; v gate = (sense+) + 3 v; i gate = 0 a; v ss 1 v circuit breaker offset v cbos 0.6 0.88 1.12 mv circuit breaker trip voltage, v cb = v sensecl ? v cbos severe overcurrent voltage threshold v senseoc 40 50 mv v iset = 1.0 v; v flb > 1.1 v; v ss 2 v 9.5 13.0 mv v iset = 0.25 v; v flb > 1.1 v; v ss 2 v short glitch filter duration 90 200 ns v iset > 1.65 v; v sense driven from 18 mv to 52 mv; selectable via pmbus long glitch filter duration (default) 530 900 ns v sense driven from 18 mv to 52 mv response time with short glitch filter 180 370 ns 2 mv ov erdrive maximum severe overcurrent threshold with long glitch filter 645 1020 ns soft start (ss pin) ss pull-up current i ss ?12 ?10 ?8 a v ss = 0 v default v sensecl limit 0.5 1.25 1.8 mv when v sense reaches this level, i ss is enabled, ramping v sensecl ; v ss = 0 v ss pull-down current 100 a v ss = 1 v timer pin timer pull-up current i timerup power-on reset(por) i timeruppor ?2 ?3 ?4 a initial power-on reset; v timer = 0.5 v overcurrent (oc) fault i timerupflt ?57 ?60 ?63 a overcurrent fault; 0.2 v v timer 1 v timer pull-down current retry i timerdnrt 1.7 2 2.3 a after fault when gate is off; v timer = 0.5 v hold i timerdnhold 100 a holds timer at 0 v when inactive; v timer = 0.5 v timer retry/oc fault current ratio 3.33 3.8 % defines the limits of the autoretry duty cycle timer high threshold v timerh 0.98 1.0 1.02 v timer low threshold v timerl 0.18 0.2 0.22 v foldback (flb pin) flb and pwrgd threshold v flbth 1.08 1.1 1.12 v flb rising; v iset = 1.0 v input current i flb 100 na v flb 1.0 v; v iset = 1.25 v 100 na v vcap v flb 20 v hysteresis current 1.7 2.3 a internal hysteresis voltage 1.9 3.1 mv vo ltage drop across the internal 1.3 k resistor power-good glitch filter pwrgd gf 0.3 0.7 1 s 50 mv overdrive minimum foldback clamp 200 mv accuracies included in total sense voltage accuracies vout pin input current 20 a vout = 20 v latch pin output low voltage v ol_latch 0.4 v i latch = 1 ma 1.5 v i latch = 5 ma leakage current 100 na v latch 2 v; latch output high-z 1 a v latch = 20 v; latch output high-z enable pin no internal pull-up present on this pin leakage current 100 na v gpo2 2 v 1 a v gpo2 = 20 v input high voltage v ih 1.1 v input low voltage v il 0.8 v
adm1276 rev. 0 | page 6 of 48 parameter symbol min typ max unit test conditions/comments gpo2/ alert2 pin output low voltage v ol_gpo2 0.4 v i gpo2 = 1 ma 1.5 v i gpo2 = 5 ma leakage current 100 na v gpo2 2 v; gpo output high-z 1 a v gpo2 = 20 v; gpo output high-z pwrgd pin output low voltage v ol_pwrgd 0.4 v i pwrgd = 1 ma 1.5 v i pwrgd = 5 ma vcc that guarantees valid output 1 v i sink = 100 a; v ol_pwrgd = 0.4 v leakage current 100 na v pwrgd 2 v; pwrgd output high-z 1 a v pwrgd = 20 v; pwrgd output high-z current and voltage monitoring current sense absolute error 25 mv input range; 128 sample averaging (unless otherwise noted) 0.2 0.7 % v sense = 20 mv; v sense+ = 12 v; t a = 0c to 65c 0.08 % v sense = 20 mv; v sense+ = 12 v; t a = 25c 1.0 % v sense = 20 mv 0.08 % v sense = 20 mv; t a = 25c 0.2 % v sense = 20 mv; t a = 0c to 65c 1.0 % v sense = 20 mv; 16 sample averaging 0.08 % v sense = 20 mv; 16 sample averaging; t a = 25c 0.2 % v sense = 20 mv; 16 sample averaging; t a = 0c to 65c 2.8 % v sense = 20 mv; 1 sample averaging 0.09 % v sense = 20 mv; 1 sample averaging; t a = 25c 0.2 % v sense = 20 mv; 1 sample averaging; t a = 0c to 65c 0.7 % v sense = 25 mv; v sense+ = 12 v 0.04 % v sense = 25 mv; v sense+ = 12 v; t a = 25c 0.15 % v sense = 25 mv; v sense+ = 12 v; t a = 0c to 65c 0.75 % v sense = 20 mv; v sense+ = 12 v 0.8 % v sense = 15 mv; v sense+ = 12 v 1.1 % v sense = 10 mv; v sense+ = 12 v 2.0 % v sense = 5 mv; v sense+ = 12 v 4.3 % v sense = 2.5 mv; v sense+ = 12 v sense+/vout absolute error 1.0 % low input range; input voltage 3 v 1.0 % high input range; input voltage 10 v adc conversion time includes time for power multiplication 237 280 s 1 sample of vin and iout; from command received to valid data in register 360 426 s 1 sample of vin, vout, and iout; from command received to valid data in register 3753 4233 s 16 samples of vin and iout averaged; from command received to valid data in register 5545 6570 s 16 samples of vin, vout, and iout averaged; from command received to valid data in register power multiplication time 14 s adr pin address set to 00 0 0.8 v connect to gnd input current for address 00 ?40 ?22 a v adr = 0 v to 0.8 v address set to 01 135 150 165 k resistor to gnd address set to 10 ?1 +1 a no connect state; maximum leakage current allowed
adm1276 rev. 0 | page 7 of 48 parameter symbol min typ max unit test conditions/comments address set to 11 2 v connect to vcap input current for address 11 3 10 a v adr = 2.0 v to vcap; must not exceed the maximum allowable current draw from vcap serial bus digital inputs (sda, scl) input high voltage v ih 1.1 v input low voltage v il 0.8 v output low voltage v ol 0.4 v i ol = 4 ma input leakage i leak-pin ?10 +10 a ?5 +5 a device is not powered nominal bus voltage v dd 2.7 5.5 v 3 v to 5 v 10% capacitance for sda, scl pins c pin 5 pf input glitch filter t sp 0 50 ns serial bus timing characteristics table 2. parameter description min typ max unit test conditions/comments f sclk clock frequency 400 khz t buf bus free time 1.3 s following th e stop condition of a read transaction 4.7 s following the stop condition of a write transaction t hd;sta start hold time 0.6 s t su;sta start setup time 0.6 s t su;sto stop setup time 0.6 s t hd;dat sda hold time 300 900 ns t su;dat sda setup time 100 ns t low scl low time 1.3 s t high scl high time 0.6 s t r scl, sda rise time 20 300 ns t f scl, sda fall time 20 300 ns timing diagram t low t buf t hd;dat t su;dat t su;sta t hd;sta t high t r t f t su;sto p s s p v ih v il v ih v il scl sda 09718-002 figure 2. serial bus timing diagram
adm1276 rev. 0 | page 8 of 48 absolute maximum ratings table 3. parameter rating vcc pin ?0.3 v to +25 v uv pin ?0.3 v to +4 v ov pin ?0.3 v to +4 v ss pin ?0.3 v to vcap + 0.3 v timer pin ?0.3 v to vcap + 0.3 v vcap pin ?0.3 v to +4 v iset pin ?0.3 v to vcap + 0.3 v latch pin ?0.3 v to +25 v scl pin ?0.3 v to +6.5 v sda pin ?0.3 v to +6.5 v adr pin ?0.3 v to vcap + 0.3 v enable pin ?0.3 v to +25 v gpo2/ alert2 pin ?0.3 v to +25 v pwrgd pin ?0.3 v to +25 v flb pin ?0.3 v to +25 v vout pin ?0.3 v to +25 v gate pin (internal supply only) 1 ?0.3 v to +36 v sense+ pin ?0.3 v to +25 v sense? pin ?0.3 v to +25 v v sense (v sense+ ? v sense? ) 0.3 v continuous current into any pin 10 ma storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature, soldering (10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja unit 20-lead lfcsp (cp-20-9) 30.4 c/w esd caution 1 the gate pin has internal clamping circuits to prevent the gate pin voltage from exceeding the maximum ratings of a mosfet with v gsmax = 20 v and internal process limits. applying a vo ltage source to this pin externally may cause irreversible damage.
adm1276 rev. 0 | page 9 of 48 pin configuration and fu nction descriptions 1 ov 2 vcap 3 iset 4 ss 5 timer latch adr enable gpo2/alert2 sda 13 14 15 12 11 flb vout gnd pwrgd scl sense+ vcc uv sense? gate 6 7 8 0 1 9 8 1 9 1 0 2 7 1 6 1 adm1275-3 top view (not to scale) pin 1 indicator notes 1. solder the exposed paddle to the board to improve thermal dissipation. the exposed paddle can be connected to ground. 09718-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 19 vcc positive supply input pin. an undervol tage lockout (uvlo) circuit resets the device when a low supply voltage is detected. gate is held low when the supply is below uvlo. during normal operation, this pin should remain greater than or equal to sense+ to ensure that spec ifications are adhered to. no sequencing is required. 20 uv undervoltage input pin. an external re sistor divider is used from the supply to this pin to allow an internal comparator to detect whether th e supply is under the uv limit. 1 ov overvoltage input pin. an external resistor divider is us ed from the supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. 2 vcap internal regulated supply. place a capacitor with a value of 1 f or greater on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin voltage. 3 iset current limit. this pin allows the current-limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. to achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from vcap. an external reference can also be used. 4 ss soft start pin. a capacitor is used on this pin to set the soft start ramp prof ile. the voltage on the ss pin controls the current sense voltage limit, which controls the inrush current profile. 5 timer timer pin. an external capacitor, c timer , sets an initial timing cycle delay and a fault delay. the gate pin is pulled low when the voltage on the timer pin exceeds the upper threshold. 6 latch latch pin. this pin signals that the device is latching off after an overcurrent fault. the device can be configured for automatic retry after latch-off by connecting this pin directly to the uv or the enable pin. 7 adr pmbus address pin. this pin can be tied to gnd, tied to vcap, remain floating, or tied low through a resistor to set four different pmbus addresses (see the device addressing section). 8 enable enable pin. this pin is a digital logic input. this inp ut must be high to allow the adm1276 hot swap controller to begin a power-up sequence. if this pin is held low, the adm1276 is prevented from powering up. there is no internal pull-up on this pin. 9 gpo2/ alert2 general-purpose digital output/alert. this is a dual functi on pin. there is no internal pull-up on this pin. the alert2 function of this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. at power-up, alert2 indicates the fet health mode by default. 10 sda serial data input/output pin. open-drain input/output. requires an external resistive pull-up. 11 scl serial clock pin. open-drain input. requires an external resistive pull-up. 12 pwrgd power-good signal. used to indicate that the supply is within tolerance. this signal is based on the voltage present on the flb pin. 13 flb foldback pin. a foldback resistor divider is placed from the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the fold back feature ensures that the power through the fet is not increased beyond the soa limits. 14 vout output voltage. this pin is used to read back the output voltage using the internal adc. 15 gnd ground pin.
adm1276 rev. 0 | page 10 of 48 pin no. mnemonic description 16 gate gate output pin. this pin is the high-side gate drive of an external n-channel fet. this pin is driven by the fet drive controller, which uses a charge pump to provide a pull-up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulati ng the gate pin. gate is held low when the supply is below uvlo. 17 sense? negative current sense input pin. a sense resistor betw een the sense+ pin and the sense? pin sets the analog current limit. the hot swap operation of the adm1276 co ntrols the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. 18 sense+ positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog curren t limit. the hot swap operation of the adm1276 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin is also used to measure the supply input voltage using the adc. n/a 1 ep exposed pad. the exposed pad is located on the undersid e of the lfcsp package. solder the exposed pad to the printed circuit board (pcb) to improve thermal dissipa tion. the exposed pad can be connected to ground. 1 n/a means not applicable.
adm1276 rev. 0 | page 11 of 48 typical performance characteristics 0 1 2 3 4 5 i cc (ma) v cc (v) 2 4 6 8 1012141618 20 +25c +85c ?40c 09718-004 figure 4. supply current (i cc ) vs. supply voltage (v cc ) 0 1 2 3 4 5 ?40 ?20 0 i cc (ma) temperature (c) v cc = 20v v cc = 12v v cc = 2.95v 20 40 60 80 09718-005 figure 5. supply current (i cc ) vs. temperature 0 2 4 6 8 10 12 14 2468 12 10 14 16 18 20 i gatedn_slow (ma) v cc (v) +25c ?40c +85c 09718-006 figure 6. gate pull-down current (i gatedn_slow ) vs. supply voltage (v cc ) 0 2 4 6 8 10 12 14 i gatedn_slow (ma) temperature (c) v cc = 12v ?40 ?200 20406080 09718-007 figure 7. gate pull-down current (i gatedn_slow ) vs. temperature 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 25 i gatedn_slow (ma) v gate (v) 09718-008 figure 8. gate pull-down current (i gatedn_slow ) vs. gate voltage (v gate ) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 2468101214161820 i gateup ( a) v cc (v) 09718-009 figure 9. gate pull-up current (i gateup ) vs. supply voltage (v cc )
adm1276 rev. 0 | page 12 of 48 0 5 10 15 20 25 30 0 5 10 15 20 25 i gateup ( a) v gate (v) v cc = 12v v cc = 2.95v 09718-010 figure 10. gate pull-up current (i gateup ) vs. gate voltage (v gate ) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 i gateup ( a) temperature (c) v cc = 12v ?40 ?20 0 20 40 60 80 09718-011 figure 11. gate pull-up current (i gateup ) vs. temperature 0 2 4 6 8 10 12 14 16 22 0 ? v gate (v) v cc (v) +85c +25c ?40c 4 6 8 10 12 14 16 18 09718-012 figure 12. gate drive voltage (v gate ) vs. supply voltage (v cc ), no load 0 2 4 6 8 10 12 14 16 ? v gate (v) v cc (v) 2 4 6 8 101214161820 +25c +85c ?40c 09718-013 figure 13. gate drive voltage (v gate ) vs. supply voltage (v cc ), 5 a load 0 2 4 6 8 10 12 14 16 ?40 ?20 0 20 40 60 ? v gate (v) temperature (c) v cc = 12v v cc = 20v v cc = 2.95v 80 09718-014 figure 14. gate drive voltage (v gate ) vs. temperature, no load ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 ?40 i ss ( a) temperature (c) v cc = 12v ?200 20406080 09718-015 figure 15. soft start pull-up current (i ss ) vs. temperature
adm1276 rev. 0 | page 13 of 48 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 i timerupflt (a) ?40 temperature (c) ?200 20406080 v cc = 12v 09718-016 figure 16. timer pull-up current, overcurrent fault (i timerupflt ) vs. temperature ?200 20406080 ?10 ?8 ?6 ?4 ?2 0 i timeruppor ( a) ?40 temperature (c) v cc = 12v 09718-017 figure 17. timer pull-up current, power-on reset (i timeruppor ) vs. temperature ?40 ?200 20406080 0 1.5 3.0 4.5 i timerdnrt ( a) v cc = 12v temperature (c) 09718-018 figure 18. timer pull-down current, retry (i timerdnrt ) vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 1100 timer threshold (mv) ?40 temperature (c) ?20 0 20 40 60 80 low threshold (v cc = 12v) high threshold (v cc = 12v) 09718-019 figure 19. timer thresholds vs. temperature ?40 ?20 0 temperature (c) 20 40 60 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 foldback threshold (v) 2.95v 12v 20v 09718-020 figure 20. foldback threshold vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 foldback hysteresis current (a) 2.95v 12v 20v ?40 ?20 0 temperature (c) 20 40 60 80 09718-021 figure 21. foldback hysteres is current vs. temperature
adm1276 rev. 0 | page 14 of 48 0 20 40 60 80 100 120 140 160 180 200 220 240 foldback clamp (mv) temperature (c) v cc = 12v ?40 ?200 20406080 09718-022 figure 22. foldback clamp vs. temperature 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 22 0 oc response time (ns) v cc (v) 4 6 8 1012141618 +85c ?40c +25c 09718-023 figure 23. severe overcurrent response time vs. supply voltage (v cc ), v iset = 0.25 v 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 oc response time (ns) v cc (v) 22 0 4 6 8 1012141618 +85c +25c ?40c 09718-024 figure 24. severe overcurrent response time vs. supply voltage (v cc ), v iset = 1 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 22 v cbos (mv) v cc (v) 0 ?40c +85c +25c 4 6 8 10 12 14 16 18 09718-025 figure 25. circuit breaker offset (v cbos ) vs. supply voltage (v cc ) 0 5 10 15 20 25 30 v sensecl (mv) temperature (c) ?40 ?200 20406080 v cc = 12v 09718-026 figure 26. hot swap sense voltage current limit (v sensecl ) vs. temperature 0 5 10 15 20 25 30 1.11.00.90.80.70.60.5 0.4 0.30.20.1 0 v sensecl (mv) v flb (v) t a = 25c 09718-027 figure 27. hot swap sense voltage current limit (v sensecl ) vs. foldback voltage (v flb )
adm1276 rev. 0 | page 15 of 48 0 5 10 15 20 25 30 35 40 45 50 v senseoc (mv) v cc (v) t a = 25c 2 4 6 8 10 12 14 16 18 20 09718-028 figure 28. severe overcurrent voltage threshold (v senseoc ) vs. supply voltage (v cc ), v iset = v vcap 15 10 5 0 20 25 30 35 40 45 50 v senseoc (mv) v cc = 12v temperature (c) ?40 ?20 0 20 40 60 80 09718-029 figure 29. severe overcurrent voltage threshold (v senseoc ) vs. temperature, v iset = v vcap 0123456789101112 0 50 100 150 i sensex (a) v sensex (v) 09718-030 figure 30. sense+/sense? input current (i sensex ) vs. voltage (v sensex ) 0 5 10 15 20 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ? v gate (v) i gateup (a) v cc = 2.95v v cc = 12v v cc = 20v 09718-031 figure 31. gate drive voltage (v gate ) vs. gate pull-up current (i gateup ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 012345678910 v ol_pwrgd (v) i ol (ma) v cc = 2.95v v cc = 12v 09718-032 figure 32. pwrgd pin, v ol vs. i ol 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v ol (v) v cc = 2.95v v cc = 12v 012345678910 i ol (ma) 09718-033 figure 33. latch and gpo2/ alert2 digital outputs, v ol vs. i ol
adm1276 rev. 0 | page 16 of 48 0 0.5 1.0 1.5 2.0 2.5 3.0 ?25 ?20 ?15 ?10 ?5 0 5 v adr (v) i adr (a) 00 decode 01 decode 10 decode 11 decode 09718-037 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 v vcap (v) i vcap (a) +85c +25c ?40c 09718-034 figure 34. vcap voltage (v vcap ) vs. vcap load (i vcap ) figure 37. adr pin voltage (v adr ) vs. current (i adr ) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 ?40 ?20 20 40 60 08 uv threshold (mv) temperature (c) v cc = 12v 0 09718-035 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 accuracy ( % ) sense voltage (mv) 16 averaging 128 averaging 09718-038 figure 38. worst-case current sense power monitor error vs. current sense voltage (v sense ), 0c to 65c, v sense+ = 12 v figure 35. uv threshold (uv th ) vs. temperature ?40 temperature (c) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 ov threshold (mv) v cc = 12v ?20 20 40 60 08 0 09718-036 figure 36. ov threshold (ov th ) vs. temperature
adm1276 rev. 0 | page 17 of 48 typical application circuit q 1 gate sense+ timer timer adm1276 gnd r sense sense? vcc v cp 2v to 20v 2.95v to 20v vcap iout uv ov 1.0v 1.0v vout vout 12-bit adc scl sda adr sense+ iout ldo charge pump timeout gpo2/alert2 pwrgd latch timer on timer on v cbos ss current limit flb iset timeout current- limit control ref select 1.0v gate drive/ logic logic and pmbus 50 + + ? ? + ? + ? 09718-039 figure 39. typical application circuit
adm1276 rev. 0 | page 18 of 48 theory of operation when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. these transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. the adm1276 is designed to control the powering on and off of a system in a controlled manner, allowing a board to be removed from, or inserted into, a live backplane by protecting it from excess currents. the adm1276 can reside on the backplane or on the removable board. powering the adm1276 a supply voltage from 2.95 v to 20 v is required to power the adm1276 via the vcc pin. the vcc pin provides the majority of the bias current for the device; the remainder of the current needed to control the gate drive and best regulate the v gs voltage is supplied by the sense+ pin. to ensure correct operation of the adm1276, the voltage on the vcc pin must be greater than or equal to the voltage on the sense+ pin. no sequencing of the vcc and sense+ rails is necessary. the sense+ pin can be as low as 2 v for normal operation provided that a voltage of at least 2.95 v is connected to the vcc pin. in most applications, both the vcc and sense+ pins are connected to the same voltage rail, but they are con- nected via separate traces to prevent accuracy loss in the sense voltage measurement (see figure 40 ). 2.95v to 20v r sense q 1 sense? gnd gate vcc sense+ adm1276 09718-040 figure 40. powering the adm1276 to protect the adm1276 from unnecessary resets due to transient supply glitches, an external resistor and capacitor can be added, as shown in figure 41 . choose the values of these components so as to provide a time constant that can filter any expected glitches. the resistor should, however, be small enough to keep voltage drops due to quiescent current to a minimum. unless a resistor is used to limit the inrush current, do not place a supply decoupling capacitor on the rail before the fet. 2.95v to 20v r sense q 1 sense? gnd gate vcc 330nf sense+ 22? adm1276 09718-041 figure 41. transient glitch protection using an rc network current sense inputs the load current is monitored by measuring the voltage drop across an external sense resistor, r sense (see figure 42 ). an internal current sense amplifier provides a gain of 50 to the voltage drop detected across r sense . the result is compared to an internal reference and used by the hot swap control logic to detect when an overcurrent condition occurs. r sense q 1 sense? gnd gate vcc sense+ adm1276 over- current reference 50 + + ? ? 09718-042 figure 42. hot swap current sense amplifier the sense inputs may be connected to multiple parallel sense resistors, which can affect the voltage drop detected by the adm1276. the current flowing through the sense resistors creates an offset, resulting in reduced accuracy. to achieve better accuracy, the averaging resistors sum the current from the nodes of each sense resistor, as shown in figure 43 . the typical value for the averaging resistors is 10 . the averaging resistors are chosen to balance the input current to both sense pins to within 5 a. this ensures that the same offset is seen by both sense inputs.
adm1276 rev. 0 | page 19 of 48 q 1 sense? gnd gate vcc sense+ bias current 2.95 v to 20v 09718-043 figure 43. connection of multiple se nse resistors to the sense pins current-limit reference the current-limit reference voltage determines the load current level to which the adm1276 limits the current during an over- current event. this reference voltage is compared to the gained-up current sense voltage to determine whether the limit is reached. an internal current-limit reference selector block continuously compares the iset, soft start, and foldback voltages to determine which voltage is the lowest at any given time; the lowest voltage is used as the current-limit reference. this ensures that the pro- grammed current limit, iset, is used in normal operation, and that the soft start and foldback features reduce the current limit when required during startup and/or fault conditions. r sense q 1 sense? gnd gate vcc iset ss flb sense+ adm1276 over- current 50 09718-044 figure 44. current-limit reference selection the foldback and soft start voltages vary during different modes of operation and are, therefore, clamped to minimum levels of 200 mv and 100 mv, respectively, to prevent zero current flow due to the current limit being too low. figure 45 provides an example of how the soft start, foldback, and iset voltages interact during startup as the adm1276 is enhancing the fet and charging the load capacitances. depending on how the soft start and fold- back features are configured, the hand-off point can vary to ensure that the fet is being operated within the correct limits. ss flb iset 1v 0.2v 0.1v v t current-limit reference 09718-045 figure 45. interaction of soft start, foldback, and iset current limits setting the current limit (iset) the maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. however, as currents become larger, the sense resistor requirements become smaller, and resolution can be difficult to achieve when selecting the appropriate sense resistor. the adm1276 provides an adjustable current sense voltage limit to handle this issue. the device allows the user to program the required current sense voltage limit from 5 mv to 25 mv. the default value of 20 mv is achieved by connecting the iset pin directly to the vcap pin. this configures the device to use an internal 1 v reference, which equates to 20 mv at the sense inputs (see figure 46 ). adm1276 vcap iset c1 gnd 09718-046 figure 46. fixed 20 mv current sense limit to program the sense voltage from 5 mv to 25 mv, a resistor divider is used to set a reference voltage on the iset pin (see figure 47 ).
adm1276 rev. 0 | page 20 of 48 adm1276 gnd vcap iset c1 r1 r2 09718-047 figure 47. adjustable 5 mv to 25 mv current sense limit the vcap pin has a 2.7 v internal generated voltage that can be used to set a voltage at the iset pin. assuming that v iset equals the voltage on the iset pin, size the resistor divider to set the iset voltage as follows: v iset = v sense 50 where v sense is the current sense voltage limit. the vcap rail can also be used as the pull-up supply for setting the i 2 c address. do not use the vcap pin for any other purpose. to guarantee accuracy specifications, do not load the vcap pin by more than 100 a. soft start a capacitor connected to the ss pin determines the inrush current profile. before the fet is enabled, the output voltage of the current-limit reference selector block is clamped at 100 mv. this, in turn, holds the hot swap sense voltage current limit, v sensecl , at approximately 2 mv. when the fet receives a request to turn on, the ss pin is held at ground until the voltage between the sense+ and sense? pins (v sense ) reaches the circuit breaker voltage, v cb . v cb = v sensecl ? v cbos where v cbos is typically 0.88 mv, making v cb = 1.12 mv. when the load current generates a sense voltage equal to v cb , a 10 a current source is enabled, which charges the ss capa- citor and results in a linear ramping voltage on the ss pin. the current-limit reference also ramps up accordingly, allowing the regulated load current to ramp up while avoiding sudden transients during power-up. the ss capacitor value is given by iset ss ss v ti c = where: i ss = 10 a. t = ss ramp time. for example, a 10 nf capacitor gives a soft start time of 1 ms. note that the ss voltage may intersect with the flb (foldback) voltage, and the current-limit reference may change to follow flb (see figure 45 ). this change has minimal impact on startup because the output voltage rises at a similar rate to the ss voltage. gate sense+ adm1276 gnd sense? 50 ss current limit flb iset timeout current limit control ref select 1.0v current limit vcap 10a gate drive/ logic + + ? ? v cp 09718-048 figure 48. soft start foldback foldback is a method to actively reduce the current limit as the voltage drop across the fet increases. it keeps the power across the fet to a minimum during power-up, overcurrent, or short- circuit events. it also avoids the need to oversize the fet to accommodate worst-case conditions, resulting in board size and cost savings. the adm1276 detects the voltage drop across the fet by looking at a resistor divided version of the output voltage. it is assumed that the supply voltage remains constant and within tolerance. the device, therefore, relies on the principle that the drain of the fet is at the maximum expected supply voltage, and that the magnitude of the output voltage is relative to that of the v ds of the fet. using a resistor divider from the output voltage to the flb pin, a relationship from v out , and thus v ds , to v flb can be derived. design the resistor divider to output a voltage equal to iset when v out falls below the desired level. this should be well below the working tolerance of the supply rail. as v out continues to drop, the current-limit reference follows v flb because it is now the lowest voltage input to the current-limit reference selector block. this results in a reduction of the current limit and, therefore, the regulated load current. to prevent complete current flow restriction, a clamp becomes active when the current-limit reference reaches 200 mv. the current limit cannot drop below this level. to suit the soa characteristics of a particular fet, the required minimum current for this clamp varies from design to design. however, the current-limit reference fixes this clamp at 200 mv, which equates to 4 mv at the sense resistor. therefore, the main iset voltage can be adjusted to align this clamp to the required percentage current reduction. for example, if iset equals 0.8 v, the clamp can be set at 25% of the maximum current.
adm1276 rev. 0 | page 21 of 48 timer the timer pin handles several timing functions with an external capacitor, c timer . the two comparator thresholds are v timerl (0.2 v) and v timerh (1 v). there are four timing current sources: a 3 a pull-up, a 60 a pull-up, a 2 a pull-down, and a 100 a pull-down. these current and voltage levels, together with the value of c timer chosen by the user, determine the initial timing cycle time, the fault current-limit time, and the hot swap retry duty cycle. the timer pin capacitor value is determined using the following equation: c timer = ( t on 60 a)/ v timerh where t on is the time that the fet is allowed to spend in regu- lation at the set current limit. the choice of fet is based on matching this time with the soa requirements of the fet. foldback can be used to simplify the selection. when vcc is connected to the backplane supply, the internal supply of the adm1276 must be charged up. in a very short time, the internal supply is fully charged up and, because the undervoltage lockout (uvlo) voltage is exceeded at vcc, the device emerges from reset. during this first short reset period, the gate and timer pins are both held low. the adm1276 then goes through an initial timing cycle. the timer pin is pulled high with 3 a. when the timer pin reaches the v timerh threshold (1.0 v), the first portion of the initial timing cycle is complete. the 100 a current source then pulls down the timer pin until it reaches v timerl (0.2 v). the initial timing cycle duration is related to c timer by the following equation: a100 ) ( a3 ? ? ? ? ? ? ? timer timerl timerh timer timerh initial cvv cv t for example, a 100 nf capacitor results in a delay of approxi- mately 34 ms. if the uv and ov inputs indicate that the supply is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot swap operation. when the voltage across the sense resistor reaches the circuit breaker trip voltage, v cb , the 60 a timer pull-up current is activated, and the gate begins to regulate the current at the current limit. this initiates a ramp-up on the timer pin. if the sense voltage falls below this circuit breaker trip voltage before the timer pin reaches v timerh , the 60 a pull-up is disabled and the 2 a pull-down is enabled. the circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. there is a small circuit breaker offset, v cbos , which means that the timer actually starts a short time before the current reaches the defined current limit. however, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 a pull-up remains active and the fet remains in regulation. this allows the timer pin to reach v timerh and initiate the gate shutdown. on the adm1276, the latch pin is pulled low immediately. in latch-off mode, the timer pin is switched to the 2 a pull-down when it reaches the v timerh threshold. the latch pin remains low. while the timer pin is being pulled down, the hot swap controller remains off and cannot be turned back on. when the voltage on the timer pin goes below the v timerl threshold, the hot swap controller can be reenabled by toggling the uv pin or by using the pmbus operation command to toggle the on bit from on to off and then on again. hot swap retry duty cycle the adm1276 turns off the fet after an overcurrent fault and then uses the capacitor on the timer pin to provide a delay before automatically retrying the hot swap operation. to configure the adm1276 for autoretry mode, the latch pin is tied to either the uv pin or to the enable pin. note that a pull-up resistor is required on the latch pin. when an overcurrent fault occurs, the capacitor on the timer pin is charged with a 60 a pull-up current. when the timer pin reaches v timerh , the gate pin is pulled down. when the latch pin is tied to the uv pin or the enable pin for auto- retry mode, the timer pin is pulled down with a 2 a current sink. when the timer pin reaches v timerl (0.2 v), it automatically restarts the hot swap operation. the duty cycle of this automatic retry cycle is set by the ratio of 2 a/60 a, which approximates to being on about 4% of the time. the value of the timer capacitor determines the on time of this cycle, which is calculated as follows: t on = v timerh ( c timer /60 a) t off = ( v timerh ? v timerl ) ( c timer /2 a) a 100 nf capacitor on the timer pin gives an on time of 1.67 ms and an off time of 40 ms. the device retries indefinitely in this manner and can be disabled manually by holding the uv or enable pin low, or by disconnecting the latch pin. to pre- vent thermal stress, an rc network can be used to extend the retry time to any desired level. fet gate drive clamps the charge pump used on the gate pin is capable of driving the pin to v cc + (2 v cc ), but it is clamped to less than 14 v above the sense pins and less than 31 v. these clamps ensure that the maximum v gs rating of the fet is not exceeded.
adm1276 rev. 0 | page 22 of 48 fast response to severe overcurrent the adm1276 features a separate high bandwidth current sense amplifier that is used to detect a severe overcurrent that is indicative of a short-circuit condition. a fast response time allows the adm1276 to handle events of this type that could otherwise cause catastrophic damage if not detected and acted on very quickly. the fast response circuit ensures that the adm1276 can detect an overcurrent event at approximately 200% to 250% of the normal current limit (iset) and can respond to and control the current within 1 s, in most cases. undervoltage and overvoltage the adm1276 monitors the supply voltage for undervoltage (uv) and overvoltage (ov) conditions. the uv and ov pins are connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 1 v voltage reference. figure 49 illustrates the voltage monitoring input connections. an external resistor network divides the supply voltage for moni- toring. an undervoltage event is detected when the voltage connected to the uv pin falls below 1 v, and the gate is shut down using the 10 ma pull-down device. similarly, when an overvoltage event occurs and the voltage on the ov pin exceeds 1 v, the gate is shut down using the 10 ma pull-down device. gate sense+ adm1276 gnd sense? gate drive r sense q1 v in 1v 1v iout uv ov vcc 50 +? ? + + ? 09718-049 figure 49. undervoltage and overvoltage supply monitoring enable input the adm1276 provides a dedicated enable digital input pin. the enable pin allows the adm1276 to remain off by using a hardware signal, even when the voltage on the uv pin is above 1.0 v and the voltage on the ov pin is less than 1.0 v. although the uv pin can be used to provide a digital enable signal, using the enable pin for this purpose means that the ability to monitor for undervoltage conditions is not lost. in addition to the conditions for the uv and ov pins, the adm1276 enable input pin must be high for the device to begin a power-up sequence. a similar function can be achieved using the uv pin directly. alternatively, if the uv divider function is still required, the configuration shown in figure 50 can be used. v in r1 d1 r2 en uv system control adm1276 09718-050 figure 50. using the uv pin as an enable diode d1 prevents the external driver pull-up from affecting the uv threshold. select diode d1 using the following criteria: ( v f d1 ) + (v ol en ) << 1.0 v ( i f = v in / r1 ) ensure that the en sink current does not exceed the specified v ol value. if the open-drain device has no pull-up, the diode is not required. power good the power good (pwrgd) output can be used to indicate whether the output voltage is above a user-defined threshold and can, therefore, be considered good. the pwrgd output is derived using the flb resistor network, composed of r1 and r2 (see figure 51). the pwrgd pin is an open-drain output that pulls low when the voltage at the flb pin is lower than 1.1 v iset (power bad). when the voltage at the flb pin is above this threshold (indicating that the output voltage has risen), the open-drain pull-down is disabled, allowing pwrgd to be pulled high. pwrgd is guaranteed to be in a valid state for vcc 1 v. hysteresis on the flb pin is provided by a 2 a internal current source that is switched on when the v flb input voltage exceeds the input threshold. the current source is disconnected when v out drops below the foldback threshold voltage minus the hysteresis voltage. resistor r3 is internal to the adm1276. the hysteresis voltage at the flb pin can be varied by adjusting the parallel combination of resistor r1 and resistor r2. v out flb 2 a r1 r2 r3 pwrgd 1.3k ? switch is on when comparator output is high 1.1 v iset 09718-051 figure 51. generation of pwrgd signal
adm1276 rev. 0 | page 23 of 48 vout measurement the vout pin on the adm1276 can be used to provide an alternate voltage for the power monitor to measure. the user can choose to measure the voltage at the sense+ pin or the voltage at the vout pin, using either the low or high input voltage range. if the vout pin is to be used to measure the output voltage after the fet, insert a 1 k resistor in series between the source of the fet and the vout pin. this resistor provides some separa- tion between the adm1276 and the fet source during a fault condition; thus, adm1276 operation is not affected. fet health the adm1276 provides a method of detecting a shorted pass fet. the fet health status can be used to generate an alert on the gpo2/ alert2 pin. by default at power-up, an alert is gener- ated on the gpo2/ alert2 pin of the adm1276 when the fet health status indicates that a bad fet is present. fet health is considered bad if all of the following conditions are true: ? the adm1276 is holding the fet off, for example, during the initial power-on cycle time. ? v sense > 2 mv. ? v gate < ~1 v, that is, less than the fet gate threshold. power monitor the adm1276 features an integrated adc that accurately meas- ures the current sense voltage, the input voltage, and (optionally) the output voltage. the measured input voltage and current being delivered to the load are multiplied to give a power value that can be read back. each power value is also added to an accumulator that can be read back to allow an external device to calculate the energy consumption of the load. the adm1276 can report the measured current, input voltage, and the output voltage. the peak_iout, peak_vin, and peak_vout commands can be used to read the highest peak current or voltage since the value was last cleared. an averaging function is provided for voltage and current that allows a number of samples to be averaged by the adm1276. this function reduces the need for postprocessing of sampled data by the host processor. the number of samples that can be averaged is 2 n , where n is in the range of 0 to 7. the power monitor current sense amplifier is bipolar and can measure both positive and negative currents. the power monitor amplifier has an input range of 25 mv. two input voltage ranges are available and can be selected using the pmbus interface: 0 v to 6 v (low input range) and 0 v to 20 v (high input range). the two basic modes of operation for the power monitor are single shot and continuous. in single shot mode, the power monitor samples the input voltage and current a number of times, depending on the averaging value selected by the user. the adm1276 returns a single value corresponding to the average voltage and current measured. when configured for continuous mode, the power monitor continuously samples voltage and current, making the most recent sample available to be read. the single shot mode can be triggered in a number of ways. the simplest is by selecting the single shot mode using the pmon_config command and writing to the convert bit using the pmon_control command. the convert bit can also be written as part of a pmbus group command. using a group command allows multiple devices to be written to as part of the same i 2 c bus transaction, with all devices executing the command when the stop condition appears on the bus. in this way, several devices can be triggered to sample at the same time.
adm1276 rev. 0 | page 24 of 48 pmbus interface the i 2 c bus is a common, simple serial bus used by many devices to communicate. it defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. smbus is based on i 2 c and aims to provide a more robust and fault tolerant bus. functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus. pmbus is layered on top of smbus and, in turn, on i 2 c. using the smbus defined bus messages, pmbus defines a set of standard commands that can be used to control a device that is part of a power chain. the adm1276 command set is based upon the pmbus? power system management protocol specification , part i and part ii, revision 1.2. this version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. however, many of the standard pmbus commands can be mapped directly to the functions of a hot swap controller. part i and part ii of the pmbus standard describe the basic commands and how they can be used in a typical pmbus setup. the following sections describe how the pmbus standard and the adm1276 specific commands are used. device addressing the adm1276 is available in one model: the adm1276-3. the pmbus address is 7 bits in size. the upper 5 bits (msbs) of the address word are fixed. the base address for the adm1276 is 01000xx (0x20). the adm1276 has a single adr pin that is used to select one of four possible addresses. the adr pin connection selects the lowest two bits (lsbs) of the 7-bit address word (see table 6). table 6. pmbus addresses and adr pin connection value of address lsbs adr pin connection 00 connect to gnd 01 150 k resistor to gnd 10 no connection (floating) 11 connect to vcap smbus protocol usage all i 2 c transactions on the adm1276 are done using smbus defined bus protocols. the following smbus protocols are implemented by the adm1276: ? send byte ? receive byte ? wr ite byte ? read byte ? wr ite word ? read word ? block read packet error checking the adm1276 pmbus interface supports the use of the packet error checking (pec) byte that is defined in the smbus standard. the pec byte is transmitted by the adm1276 during a read transaction or sent by the bus host to the adm1276 during a write transaction. the adm1276 supports the use of pec with all the smbus protocols that it implements. the use of the pec byte is optional. the bus host can decide whether to use the pec byte with the adm1276 on a message- by-message basis. there is no need to enable or disable pec in the adm1276. the pec byte is used by the bus host or the adm1276 to detect errors during a bus transaction, depending on whether the trans- action is a read or a write. if the host determines that the pec byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. if the adm1276 determines that the pec byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. within a group command, the host can choose to send or not send a pec byte as part of the message to the adm1276.
adm1276 rev. 0 | page 25 of 48 smbus message formats figure 52 to figure 60 show all the smbus protocols supported by the adm1276, along with the pec variant. in these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the adm1276 is driving the bus. figure 52 to figure 60 use the following abbreviations: s is the start condition. sr is the repeated start condition. p is the stop condition. r is the read bit. w is the write bit. a is the acknowledge bit (0). a is the acknowledge bit (1). a represents the acknowledge bit. the acknowledge bit is typi- cally active low (logic 0) if the transmitted byte is successfully received by a device. however, when the receiving device is the bus master, the acknowledge bit for the last byte read is a logic 1, indicated by a . sp a aw slave address data byte s p a aw slave address data byte pec a master to slave slave to master 09718-052 figure 52. send byte and send byte with pec sp a ar slave address data byte s p a ar slave address data byte pec master to slave slave to master a 09718-053 figure 53. receive byte and receive byte with pec sa aw slave address command code data byte pa sa aw slave address command code data byte p a pec a master to slave slave to master 09718-054 figure 54. write byte and write byte with pec a slave address r data byte sr a a s a aw slave address command code pa pec sa aw slave address command code slave address p rdata byte sr a master to slave slave to master 09718-055 figure 55. read byte and read byte with pec p sa aw slave address command code data byte low a a sa aw slave address command code data byte low adata byte high data byte high a pa pec master to slave slave to master 09718-056 figure 56. write word and write word with pec
adm1276 rev. 0 | page 26 of 48 sr a slave address ar sa w slave address command code a data byte low pa a a data byte high sr a slave address ar sa w slave address command code a data byte low data byte high p pec master to slave slave to master 09718-057 figure 57. read word and read word with pec sr a slave address ar sa w slave address command code a byte count = n a data byte 1 p data byte n a data byte 2 sr a slave address ar sa w slave address command code a byte count = n a data byte 1 a data byte n p pec a data byte 2 master to slave slave to master a a 09718-058 figure 58. block read and block read with pec master to slave slave to master a low data byte a sa w device 1 address command code 1 a high data byte one or more data bytes a low data byte a sr a w device 2 address command code 2 a high data byte one or more data bytes a low data byte a sr a w device n address command code n ap high data byte one or more data bytes 09718-059 figure 59. group command master to slave slave to master a pec 1 p alow data byte a sa w device 1 address command code 1 a high data byte one or more data bytes a pec 2 alow data byte a sr a w device 2 address command code 2 a high data byte one or more data bytes a pec n alow data byte a sr a w device n address command code n a high data byte one or more data bytes 09718-060 figure 60. group command with pec group commands the pmbus standard defines what are known as group commands. group commands are single bus transactions that send commands or data to more than one device at the same time. each device is addressed separately, using its own address; there is no special group command address. a group command transaction can contain only write commands that send data to a device. it is not possible to use a group command to read data from devices. f rom an i 2 c protocol point of view, a normal write command consists of the following: ? i 2 c start condition. ? slave address bits and a write bit (followed by an acknowledge from the slave device). ? one or more data bytes (each of which is followed by an acknowledge from the slave device). ? i 2 c stop condition to end the transaction.
adm1276 rev. 0 | page 27 of 48 a group command differs from a nongroup command in that after the data is written to one slave device, a repeated start condition is placed on the bus followed by the address of the next slave device and data. this continues until all of the devices have been written to, at which point the stop condition is placed on the bus by the master device. the format of a group command and a group command with pec is shown in figure 59 and figure 60 . each device that is written to as part of the group command does not immediately execute the command written. the device must wait until the stop condition appears on the bus. at that point, all devices execute their commands at the same time. using a group command, it is possible, for example, to turn multiple pmbus devices on or off simultaneously. in the case of the adm1276, it is also possible to issue a power monitor command that initiates a conversion, causing multiple adm1276 devices to sample together at the same time. hot swap control commands operation command the gate pin that drives the fet is controlled by a dedicated hot swap state machine. the uv and ov input pins, the timer and ss pins, and the current sense all feed into the state machine and they control when and how strongly the gate is turned off. it is also possible to control the hot swap gate output using commands over the pmbus interface. the operation command can be used to request the hot swap output to turn on. however, if the uv pin indicates that the input supply is less than required, the hot swap output is not turned on, even if the operation command indicates that the output should be enabled. if the operation command is used to disable the hot swap output, the gate pin is held low, even if all hot swap state machine control inputs indicate that it can be enabled. the default state of bit 7 (also named the on bit) of the operation command is 1; therefore, the hot swap output is always enabled when the adm1276 emerges from uvlo. if the on bit is never changed, the uv input or the enable input is the hot swap master on/off control signal. by default at power-up, the operation command is disabled and must be enabled using the device_config command. this prevents inadvertent shutdowns of the hot swap controller by software. if the on bit is set to 0 while the uv signal is high, the hot swap output is turned off. if the uv signal is low or if the ov signal is high, the hot swap output is already off and the status of the on bit has no effect. if the on bit is set to 1, the hot swap output is requested to turn on. if the uv signal is low or if the ov signal is high, setting the on bit to 1 has no effect, and the hot swap output remains off. it is possible to determine at any time whether the hot swap output is enabled using the status_byte or the status_word command (see the status commands section). the operation command can also clear any latched faults in the status registers. to clear latched faults, set the on bit to 0 and then reset it to 1. device_config command the device_config command configures certain settings within the adm1276, for example, enabling or disabling foldback in the hot swap controller, or modifying the duration of the severe overcurrent glitch filter. this command is also used to configure the polarity of the second iout current warnings. the operation command is disabled at power-up. if the operation command is received, the adm1276 responds with a no acknowledge. to allow use of the operation command, the operation_cmd_en bit must be set via the device_config command. power_cycle command the power_cycle command can be used to request that the adm1276 be turned off for ~4 seconds and then turned back on. this command can be useful if the processor that controls the adm1276 is also powered off when the adm1276 is turned off. this command allows the processor to request that the adm1276 turn off and on again as part of a single command. adm1276 information commands capability command the capability command can be used by host processors to determine the i 2 c bus features that are supported by the adm1276. the features that can be reported include the max- imum bus speed, whether the device supports the packet error checking (pec) byte, and the smbalert reporting function. pmbus_revision command the pmbus_revision command reports the version of part i and part ii of the pmbus standard. mfr_id, mfr_model, and mfr_revision commands the mfr_id, mfr_model, and mfr_revision commands return ascii strings that can be used to facilitate detection and identification of the adm1276 on the bus. these commands are read using the smbus block read message type. this message type requires that the adm1276 return a byte count corresponding to the length of the string data that is to be read back. status commands the adm1276 provides a number of status bits that are used to report faults and warnings from the hot swap controller and the power monitor. these status bits are located in six different registers that are arranged in a hierarchy. the status_byte and status_word commands provide 8 bits and 16 bits of high level information, respectively. the status_byte and status_word commands contain the most important status
adm1276 rev. 0 | page 28 of 48 bits, as well as pointer bits that indicate whether any of the four other status registers need to be read for more detailed status information. i n the adm1276, a particular distinction is made between faults and warnings. a fault is always generated by the hot swap controller and is defined by hardware component values. three events can generate a fault: ? overcurrent condition that causes the hot swap timer to time out. ? overvoltage condition on the ov pin. ? undervoltage condition on the uv pin. when a fault occurs, the hot swap controller always takes some action, usually to turn off the gate pin, which is driving the fet. a fault can also generate an smbalert on the gpo2/ alert2 pin. all warnings in the adm1276 are generated by the power monitor, which samples the voltage and current and then compares these measurements to the threshold values set by the various limit commands. a warning has no effect on the hot swap controller, but it may generate an smbalert on the gpo2/ alert2 output pin. when a status bit is set, it always means that the status condition fault or warningis active or was active at some point in the past. when a fault or warning bit is set, it is latched until it is explicitly cleared using either the operation or the clear_faults command. some other status bits are live, that is, they always reflect a status condition and are never latched. status_byte and status_word commands the status_byte and status_word commands can be used to obtain a snapshot of the overall part status. these commands indicate whether it is necessary to read more detailed information using the other status commands. the low byte of the word returned by the status_word command is the same byte returned by the status_byte command. the high byte of the word returned by the status_word command provides a number of bits that can be used to determine which of the other status commands needs to be issued to obtain all active status bits. status_input command the status_input command returns a number of bits relating to voltage faults and warnings on the input supply. status_vout command the status_vout command returns a number of bits relating to voltage faults and warnings on the output supply. status_iout command the status_iout command returns a number of bits relating to current faults and warnings on the output supply. status_mfr_specific command the status_mfr_specific command is a standard pmbus command, but the contents of the byte returned are specific to the adm1276. clear_faults command the clear_faults command is used to clear fault and warnings bits when they are set. fault and warnings bits are latched when they are set. in this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred. if the clear_faults command is issued and the fault or warning condition is no longer active, the status bit is cleared. if the condition is still activefor example, if an input voltage is below the undervoltage threshold of the uv pinthe clear_faults command attempts to clear the status bit, but that status bit is immediately set again. gpo and alert pin setup commands a multipurpose pin is provided on the adm1276: gpo2/ alert2 . the gpo2/ alert2 pin can be configured over the pmbus in one of three output modes, as follows: ? general-purpose digital output. ? output for generating an smbalert when one or more fault/warning status bits become active in the pmbus status registers. ? digital comparator. in digital comparator mode, the current, voltage, and power warning thresholds are compared to the values read or calculated by the adm1276. the comparison result sets the output high or low according to whether the value is greater or less than the warning threshold that has been set. for an example of how to configure this pin to generate an smbalert and how to respond and clear the condition, see the example use of smbus alert response address section. alert2_config command using combinations of bit masks, the alert2_config command can be used to select the status bits that, when set, generate an smbalert signal to a processor, or control the digital comparator mode. they can also be used to set a gpo mode on the gpo2/ alert2 pin, so that it is under software control. if this mode is set, the smbalert masking bits are ignored. power monitor commands the adm1276 provides a high accuracy, 12-bit current and voltage power monitor. the power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single shot mode with a number of different sample averaging options.
adm1276 rev. 0 | page 29 of 48 t he power monitor can measure the following quantities: ? input voltage (vin). ? output voltage (vout). ? output current (iout). t he following quantities are then calculated: ? input power (pin). ? input energy (ein). pmon_config command the power monitor can run in a number of different modes with different input voltage range settings. the pmon_config command is used to set up the power monitor. t he settings that can be configured are as follows: ? single shot or continuous sampling. ? vout sampling enable/disable. ? volt age i nput range. ? current and voltage sample averaging. modifying the power monitor settings while the power monitor is sampling is not recommended. to ensure correct operation of the device and to avoid any potential spurious data or the generation of status alerts, stop the power monitor before any of these settings are changed. pmon_control command power monitor sampling can be initiated via hardware or via software using the pmon_control command. this command can be used with single shot or continuous mode. read_vin, read_vout, and read_iout commands the adm1276 power monitor measures the voltage developed across the sense resistor to provide a current measurement. the input voltage from the sense+ pin is always measured, and the output voltage present on the vout pin is available if enabled with the pmon_config command. read_pin, read_pin_ext, read_ein, and read_ein_ext commands the 12-bit vin input voltage and 12-bit iout current measure- ment values are multiplied by the adm1276 to give the input power value. this is accomplished by using fixed point arithmetic, and produces a 24-bit value. it is assumed that the numbers are in the 12.0 format, meaning that there is no fractional part. note that only positive iout values are used to avoid returning a negative power. this 24-bit value can be read from the adm1276 using the read_pin_ext command, where the most significant bit (msb) is always a zero because pin_ext is a twos complement binary value that is always positive. the sixteen most significant bits of the 24-bit value are used as the value for pin. the msb of the 16-bit pin word is always zero, as pin is a twos complement binary value, that is always positive. each time a power calculation is done, the 24-bit power value is added to a 24-bit energy accumulator register. this is a twos complement representation as well, so the msb is always zero. each time this energy accumulator register rolls over from 0x7fffff to 0x000000, a 16-bit rollover counter is incremented. the rollover counter is straight binary, with a maximum value of 0xffff before it rolls over. a 24-bit straight binary power sample counter is also incremented by 1 each time a power value is calculated and added to the energy accumulator. these registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the adm1276. a bus host can read these values, and by calculating the delta in the energy accumulated, the delta in the number of samples, and the time delta since the last read, the host can calculate the average power since the last read, as well as the energy consumed since then. the time delta is calculated by the bus host based on when it sends its commands to read from the device, and is not provided by the adm1276. to avoid loss of data, the bus host must read at a rate that ensures the rollover counter does not wrap around more than once, and if the counter does wrap around that the next value read for pin is less than the previous one. the read_ein command returns the top 16 bits of the energy accumulator, the lower eight bits of the rollover counter, and the full 24 bits of the sample counter. the read_ein_ext command returns the full 24 bits of the energy accumulator, the full 16 bits of the rollover counter, and the full 24 bits of the sample counter. the use of the longer rollover counter means that the time interval between reads of the part can be increased from seconds to minutes, without losing any data. peak_iout, peak_vin, pe ak_vout, and peak_pin commands in addition to the standard pmbus commands for reading voltage and current, the adm1276 provides commands that can report the maximum peak voltage, current, or power value since the peak value was last cleared. the peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. individual peak values are cleared by writing a 0 value with the corresponding command. warning limit setup commands the adm1276 power monitor can monitor a number of different warning conditions simultaneously and report any current or voltage values that exceed the user-defined thresholds using the status commands.
adm1276 rev. 0 | page 30 of 48 all comparisons performed by the power monitor require the measured value to be strictly greater or less than the threshold value. at power-up, all threshold limits are set to either minimum scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage or overcurrent or overpower conditions). this effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values. vin_ov_warn_limit an d vin_uv_warn_limit commands the vin_ov_warn_limit and vin_uv_warn_limit commands are used to set the ov and uv thresholds on the input voltage, as measured at the sense+ pin. vout_ov_warn_limit and vout_uv_warn_limit commands the vout_ov_warn_limit and vout_uv_warn_ limit commands are used to set the ov and uv thresholds on the output voltage, as measured at the vout pin. iout_oc_warn_limit command the iout_oc_warn_limit command sets the oc threshold for the current flowing through the sense resistor. iout_warn2_limit command the iout_warn2_limit command provides a second current warning threshold that can be programmed. the polarity of this warning can be set to overcurrent or undercurrent using the device_config command. pin_op_warn_limit command the pin_op_warn_limit command is used to set the overpower threshold for the power delivered to the load. pmbus direct format conversion the adm1276 uses the pmbus direct format internally to represent real-world quantities such as voltage, current, and power values. a direct format number takes the form of a 2-byte, twos complement, binary integer value. it is possible to convert in real-world quantities. equation 1 converts from real-world quantities to pmbus direct values, and equation 2 converts pmbus direct format values to real-world values. y = ( mx + b ) 10 r (1) x = 1/ m ( y 10 ?r ? b ) (2) where: y is the value in pmbus direct format. x is the real-world value. m is the slope coefficient, a 2-byte, twos complement integer. b is the offset, a 2-byte, twos complement integer. r is a scaling exponent, a 1-byte, twos complement integer. the same equations are used for voltage, current, and power conversions, the only difference being the values of the m, b, and r coefficients that are used. table 7 lists all the coefficients required for the adm1276. the coefficients shown are independent of the value of the external sense resistor used in a given application. this means that an additional calculation must be performed to take the sense resistor value into account when converting to or from a real- world current or power value. the current sense voltage coefficients shown in table 7 convert between the voltage that appears across the sense resistor(s), expressed in millivolts, and the direct format value that is used by the adm1276 as a threshold or reported as a current measurement. example 1. iout_oc_warn_limit requires a current-limit value expressed in direct format. if the required current limit is 10 a, and the sense resistor is 2 m, then the first step is to determine the current sense voltage. this is simply v = ir, giving 20 mv in this case. using equation 1, and expressing x, in units of millivolts y = ((807 20) + 20,475) 10 ?1 y = 3661.5 = 3662 (rounded up to integer form) writing a value of 3662 with the iout_oc_warn_limit command sets an overcurrent warning at 10 a. example 2. the read_iout command returns a direct format value of 3339 representing the current flowing through a sense resistor of 1 m. to convert this value to the current sense voltage, use equation 2 x = 1/807 (3339 10 1 ? 20,475) x = 16.00 mv to convert to current in amps, use i = v / r where r is expressed in milliohms. this means that when read_iout returns a value of 3339, 16.00 a is flowing in the sense resistor. because power is equal to voltage current, power value conversions are affected by the value of the sense resistor in a similar manner. the coefficients in table 7 can be used to convert direct format values to resistor scaled power values and vice versa, which then need to be scaled by the resistor value. when converting from real-world power to direct format, the power (in watts) is multiplied by the value of the sense resistor expressed in ohms to give the resistor scaled power value. the resistor scaled power value can then be inserted into equation 1 with the appropriate conversion coefficients to obtain the direct format value. when converting from direct format to real-world power, the direct format value is first converted with equation 2, and then
adm1276 rev. 0 | page 31 of 48 divided by the sense resistor value in ohms to obtain the real- world power in watts. there are also two input voltage ranges, thus, there are two sets of coefficients for converting to and from the power value. n ote the following: ? the same calculations that are used to convert power values also apply to the energy accumulator value returned by the read_ein command because the energy accumulator is a summation of multiple power values. ? the read_pin_ext and read_ein_ext commands return 24-bit extended precision versions of the 16-bit values returned by read_pin and read_ein. the direct format values must be divided by 256 prior to being converted with the coefficients shown in table 7 . example 3. the pin_op_warn_limit command requires a power limit value expressed in direct format. if the required power limit is 350 w and the sense resistor is 1 m, the first step is to determine the resistor scaled power value. p resscaled = p r p resscaled = 350 0.001 p resscaled = 0.35 where: p is the real-world power expressed in watts. r is the sense resistor value expressed in ohms. p resscaled is the resistor scaled version of power. using equation 1, and working with the 0 v to 20 v range, y = ((6043 0.35 + 0) 10 1 y = 21,150.5 = 21,151 (rounded up to integer form) writing a value of 21,151 with the pin_op_warn_limit command sets an overpower warning at 350 w. table 7. pmbus conversion to real-world coefficients voltage power (resistor scaled) coefficient current sense voltage 0 v to 6 v range 0 v to 20 v range 0 v to 6 v range 0 v to 20 v range m 807 6720 19,199 2115 6043 b 20,475 0 0 0 0 r ?1 ?1 ?2 +2 +1
adm1276 rev. 0 | page 32 of 48 voltage and current conversion using lsb values the direct format voltage and current values returned by the read_vin, read_vout, and read_iout commands, and the corresponding peak versions, are the data output directly by the adm1276 adc. because the voltages and currents are 12-bit adc output codes, they can also be converted to real-world values when there is knowledge of the size of the lsb on the adc. the m, b, and r coefficients defined for the pmbus conversion are required to be whole integers by the standard and have, therefore, been rounded slightly. using this alternative method, with the exact lsb values, can provide somewhat more accurate numerical conversions. to convert an adc code to current in amperes, the following formulas can be used: v sense = lsb 25 mv ( i adc ? 2048) i out = v sense /( r sense 0.001) where: v sense = (v sense+ ) ? (v sense? ). lsb 25 mv = 12.4 v. i adc is the 12-bit adc code. i out is the measured current value in amperes. r sense is the value of the sense resistor in milliohms. to convert an adc code to a voltage, the following formula can be used: v m = lsb xv ( v adc + 0.5) where: v m is the measured value in volts. v adc is the 12-bit adc code. lsb xv values are based on the voltage range (see table 8 ). table 8. voltage ranges and lsb values voltage range, lsb xv lsb magnitude 0 v to 6 v 1.488 mv 0 v to 20 v 5.208 mv to convert a current in amperes to a 12-bit value, the following formula can be used (round the result to the nearest integer): v sense = i a r sense 0.001 i code = 2048 + (v sense / lsb 25 mv ) where: v sense = (v sense+ ) ? (v sense? ). i a is the current value in amperes. r sense is the value of the sense resistor in milliohms. i code is the 12-bit adc code. lsb 25 mv = 12.4 v. to convert a voltage to a 12-bit value, the following formula can be used (round the result to the nearest integer): v code = ( v a / lsb xv ) ? 0.5 where: v code is the 12-bit adc code. v a is the voltage value in volts. lsb xv values are based on the voltage range (see table 8 ).
adm1276 rev. 0 | page 33 of 48 gpo2/ alert2 pin behavior the adm1276 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. faults and warnings a pmbus fault on the adm1276 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off. the three defined fault sources are as follows: ? undervoltage (uv) event detected on the uv pin. ? overvoltage (ov) event detected on the ov pin. ? overcurrent (oc) event that causes a hot swap timeout. faults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. when a fault occurs, a corresponding status bit is set in one or more status_xxx registers. a value of 1 in a status register bit field always indicates a fault or warning condition. fault and warning bits in the status registers are latched when set to 1. to clear a latched bit to 0 provided that the fault condition is no longer activeuse the clear_faults command or use the operation command to turn the hot swap output off and then on again. a warning is less severe than a fault and never causes a change in the state of the hot swap controller. the sources of a warning are defined as follows: ? cml: a communications error occurred on the i 2 c bus. ? hs timer was active (hsta): the current regulation was active, but did not necessarily shut the system down. ? iout oc warning from the adc. ? iout warning 2 from the adc. ? vin uv warning from the adc. ? vin ov warning from the adc. ? vout uv warning from the adc. ? vout ov warning from the adc. ? pin op warning from the vin iout calculation. generating an alert a host device can periodically poll the adm1276 using the status commands to determine whether a fault/warning is active. however, this polling is very inefficient in terms of software and processor resources. the adm1276 has a gpo2/ alert2 output pin that can be used to generate interrupts to a host processor. by default at power-up, the open-drain gpo2/ alert2 output is high impedance, so the pin can be pulled high through a resistor. the fet health bad warning is active by default on the gpo2/ alert2 pin at power-up. any one or more of the faults and warnings listed in the faults and warnings section can be enabled and cause an alert, making the gpo2/ alert2 pin active. by default, the active state of the gpo2/ alert2 pin is low. f or example, to use gpo2/ alert2 to monitor the vout uv warning from the adc, the followings steps must be performed: 1. set a threshold level with the vout_uv_warn_limit command. 2. start the power monitor sampling on vout. if a vout sample is taken that is below the configured vout uv value, the gpo2/ alert2 pin is taken low, signaling an interrupt to a processor. handling/clearing an alert when faults/warnings are configured on the gpo2/ alert2 pin, the pin becomes active to signal an interrupt to the processor. (the pin is active low, unless inversion is enabled.) the alert2 signal on the gpo2/ alert2 pin functions as an smbalert. a processor can respond to the interrupt in one of two basic ways: ? i f there is only one device on the bus, the processor can simply read the status bytes and issue a clear_faults command to clear all the status bits, which causes the deas- sertion of the gpo2/ alert2 line. if there is a persistent faultfor example, an undervoltage on the inputthe status bits remain set after the clear_faults command is executed because the fault has not been removed. however, the gpo2/ alert2 line is not pulled low unless a new fault or warning becomes active. if the cause of the smbalert is a power monitor generated warning and the power monitor is running continuously, the next sample generates a new smbalert after the clear_faults command is issued. ? if there are several devices on the bus, the processor can issue an smbus alert response address command to find out which device asserted the smbalert line. the processor can read the status bytes from that device and issue a clear_faults command. smbus alert response address the smbus alert response address (ara) is a special address that can be used by the bus host to locate any devices that need to talk to it. a host typically uses a hardware interrupt pin to monitor the smbus alert pins of a number of devices. when the host interrupt occurs, the host issues a message on the bus using the smbus receive byte or receive byte with pec protocol. the special address used by the host is 0x0c. any devices that have an smbalert signal return their own 7-bit address as the seven msbs of the data byte. the lsb value is not used and can be either 1 or 0. the host reads the device address from the received data byte and proceeds to handle the alert condition.
adm1276 rev. 0 | page 34 of 48 more than one device may have an active smbalert signal and attempt to communicate with the host. in this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. the device that succeeds disables its smbus alert signal. if the host sees that the smbus alert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addresses. example use of smbus alert response address t he full sequence of steps that occurs when an smbalert is generated and cleared is as follows: 1. a fault or warning is enabled using the alert2_config command, and the corresponding status bit for the fault or warning changes from 0 to 1, indicating that the fault or warning has just become active. 2. the gpo2/ alert2 pin becomes active (low) to signal that an smbalert is active. 3. the host processor issues an smbus alert response address command to determine which device has an active alert. 4. if there are no other active alerts from devices with lower i 2 c addresses, this device makes the gpo2/ alert2 pin inactive (high) during the no acknowledge bit period after it sends its address to the host processor. 5. if the gpo2/ alert2 pin stays low, the host processor must continue to issue smbus alert response address commands to devices to find out the addresses of all devices whose status it must check. 6. the adm1276 continues to operate with the gpo2/ alert2 pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. that is, if a status bit for a fault/warning that is enabled on the gpo2/ alert2 pin and that was not already active (equal to 1) changes from 0 to 1, a new alert is generated, causing the gpo2/ alert2 pin to become active again.
adm1276 rev. 0 | page 35 of 48 pmbus command reference command codes are in hexadecimal format. table 9. pmbus command summary command code command name smbus transaction type number of data bytes default value at reset 0x01 operation read/write byte 1 0x80 0x03 clear_faults send byte 0 not applicable 0x19 capability read byte 1 0xb0 0x42 vout_ov_warn_limit read/write word 2 0x0fff 0x43 vout_uv_warn_limit read/write word 2 0x0000 0x4a iout_oc_warn_limit read/write word 2 0x0fff 0x57 vin_ov_warn_limit read/write word 2 0x0fff 0x58 vin_uv_warn_limit read/write word 2 0x0000 0x6b pin_op_warn_limit read/write word 2 0x7fff 0x78 status_byte read byte 1 0x00 0x79 status_word read word 2 0x0000 0x7a status_vout read byte 1 0x00 0x7b status_iout read byte 1 0x00 0x7c status_input read byte 1 0x00 0x80 status_mfr_specific read byte 1 0x00 0x86 read_ein block read 1 (byte count) + 6 (data) 0x06, 0x0000, 0x00, 0x000000 0x88 read_vin read word 2 0x0000 0x8b read_vout read word 2 0x0000 0x8c read_iout read word 2 0x0000 0x97 read_pin read word 2 0x0000 0x98 pmbus_revision read byte 1 0x22 0x99 mfr_id block read 1 (byte count) + 3 (data) 0x03 + ascii adi 0x9a mfr_model block read 1 (byte co unt) + 9 (data) 0x09 + ascii adm1276-3 0x9b mfr_revision block read 1 (byte count) + 1 (data) 0x01 + ascii 0 0xd0 peak_iout read/write word 2 0x0000 0xd1 peak_vin read/write word 2 0x0000 0xd2 peak_vout read/write word 2 0x0000 0xd3 pmon_control read/write byte 1 0x01 0xd4 pmon_config read/write byte 1 0xaf 0xd6 alert2_config read/write word 2 0x8000 0xd7 iout_warn2_limit read/write word 2 0x0000 0xd8 device_config read/write byte 1 0x00 0xd9 power_cycle send byte 0 not applicable 0xda peak_pin read/write word 2 0x0000 0xdb read_pin_ext block read 1 (byte count) + 3 (data) 0x03, 0x000000 0xdc read_ein_ext block read 1 (byte count) + 8 (data) 0x08, 0x000000, 0x0000, 0x000000
adm1276 rev. 0 | page 36 of 48 operation code: 0x01, read/write byte. value after reset: 0x80. table 10. bit descriptions for operation command bits bit name settings description [7] on 0 hot swap output is disabled. 1 default. hot swap output is enabled. [6:0] reserved 0000000 always reads as 0000000. clear_faults code: 0x03, send byte, no data. capability code: 0x19, read byte. value after reset: 0xb0. table 11. bit descriptions for capability command bits bit name settings description [7] packet error checking 1 always reads as 1. packet error checking (pec) is supported. [6:5] maximum bus speed 01 always reads as 01. maximum supported bus speed is 400 khz. [4] smbalert# 1 always reads as 1. device suppor ts smbalert and alert response address (ara). [3:0] reserved 0000 always reads as 0000. vout_ov_warn_limit code: 0x42, read/write word. value after reset: 0x0fff. table 12. bit descriptions for vout_ov_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vout_ov_warn_limit overvoltage threshold for the vout pin measurement, expressed in adc codes. vout_uv_warn_limit code: 0x43, read/write word. value after reset: 0x0000. table 13. bit descriptions for vout_uv_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vout_uv_warn_limit undervoltage threshold fo r the vout pin measurement, expressed in adc codes. iout_oc_warn_limit code: 0x4a, read/write word. value after reset: 0x0fff. table 14. bit descriptions for iout_oc_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] iout_oc_warn_limit overcurrent threshold for the iout measurement through the sense resistor, expressed in adc codes. iout_warn2_limit code: 0xd7, read/write word. value after reset: 0x0000. table 15. bit descriptions fo r iout_warn2_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] iout_warn2_limit threshold for the iout measurement through the sense resistor, expressed in adc codes. this value can be either an undercurrent or an overcurrent, depending on the state of the iout_warn2_select bit that is set using the device_config command.
adm1276 rev. 0 | page 37 of 48 vin_ov_warn_limit code: 0x57, read/write word. value after reset: 0x0fff. table 16. bit descriptions fo r vin_ov_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vin_ov_warn_limit overvoltage threshold for th e sense+ pin measurement, expressed in adc codes. vin_uv_warn_limit code: 0x58, read/write word. value after reset: 0x0000. table 17. bit descriptions fo r vin_uv_warn_limit command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vin_uv_warn_limit undervoltage threshold for the sense+ pin measurement, expressed in adc codes. pin_op_warn_limit code: 0x6b, read/write word. value after reset: 0x7fff. table 18. bit descriptions for pin_op_warn_limit command bits bit name settings description [15] reserved 0 always reads as 0. [14:0] pin_op_warn_limit overpower thresh old for the vin iout power calculation. status_byte code: 0x78, read byte. value after reset: 0x00. table 19. bit descriptions for status_byte command bits bit name behavior settings description [7] reserved 0 always reads as 0. [6] hotswap_off live 0 the hot swap gate drive output is enabled. 1 the hot swap gate drive output is disabled, and the gate pin is pulled down. this can be due to, for example, an overcurrent fault that causes the adm1276 to latch off, an undervoltage condition on the uv pin, or the use of the operation comm and to turn the output off. [5] reserved 0 always reads as 0. [4] iout_oc_fault latched 0 no ov ercurrent output fault detected. 1 the hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the ti mer pin has elapsed, causing the hot swap gate drive to shut down. [3] vin_uv_fault latched 0 no undervoltage input fault detected on the uv pin. 1 an undervoltage input faul t was detected on the uv pin. [2] reserved 0 always reads as 0. [1] cml_error latched 0 no communi cations error detected on the i 2 c/pmbus interface. 1 an error was detected on the i 2 c/pmbus interface. errors detected are an unsupported command, an invalid pec byte, and an incorrectly structured message. [0] none_of_the_above live 0 no other active status bit to be reported by any other status command. 1 active status bits are waiting to be read by one or more status commands.
adm1276 rev. 0 | page 38 of 48 status_word code: 0x79, read word. value after reset: 0x0000. table 20. bit descriptions for status_word command bits bit name behavior settings description [15] vout_status live 0 there are no active status bits to be read by status_vout. 1 there are one or more active sta tus bits to be read by status_vout. [14] iout_status live 0 there are no active status bits to be read by status_iout. 1 there are one or more active sta tus bits to be read by status_iout. [13] input_status live 0 there are no active status bits to be read by status_input. 1 there are one or more active status bits to be read by status_input. [12] mfr_status live 0 there are no active status bits to be read by status_mfr_specific. 1 there are one or more active status bits to be read by status_mfr_specific. [11] power_good# live 0 the voltage on the flb pin is above the required threshold, indicating that output power is considered good. this bit is the logical inversion of the pwrgd pin on the part. 1 the voltage on the flb pin is below the required threshold, indicating that output power is considered bad. [10:8] reserved 000 always reads as 000. [7:0] status_byte this byte is the same as the byte returned by the status_byte command. status_vout code: 0x7a, read byte. value after reset: 0x00. table 21. bit descriptions for status_vout command bits bit name behavior settings description [7] reserved 0 always reads as 0. [6] vout_ov_warn latched 0 no overvoltage condition on the o utput supply detected by the power monitor. 1 an overvoltage condition on the o utput supply was detected by the power monitor. [5] vout_uv_warn latched 0 no undervoltage condition on the o utput supply detected by the power monitor. 1 an undervoltage condition on the output supply was detected by the power monitor. [4:0] reserved 00000 always reads as 00000. status_iout code: 0x7b, read byte. value after reset: 0x00. table 22. bit descriptions for status_iout command bits bit name behavior settings description [7] iout_oc_fault latched 0 no ov ercurrent output fault detected. 1 the hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the ti mer pin has elapsed, causing the hot swap gate drive to shut down. [6] reserved 0 always reads as 0. [5] iout_oc_warn latched 0 no overcurrent condition on the output supply detected by the power monitor using the iout_oc_warn_limit command. 1 an overcurrent condition was detected by the power monitor using the iout_oc_warn_limit command. [4:0] reserved 00000 always reads as 00000.
adm1276 rev. 0 | page 39 of 48 status_input code: 0x7c, read byte. value after reset: 0x00. table 23. bit descriptions for status_input command bits bit name behavior settings description [7] vin_ov_fault latched 0 no overvoltage detected on the ov pin. 1 an overvoltage was detected on the ov pin. [6] vin_ov_warn latched 0 no overvoltage condition on the input supply detected by the power monitor. 1 an overvoltage condition on the input supply was detected by the power monitor. [5] vin_uv_warn latched 0 no undervoltage condition on the in put supply detected by the power monitor. 1 an undervoltage condition on the input supply was detected by the power monitor. [4] vin_uv_fault latched 0 no undervoltage detected on the uv pin. 1 an undervoltage was detected on the uv pin. [3:1] reserved 000 always reads as 000. [0] pin_op_warn latched 0 no overpower condition on the input supply detected by the power monitor. 1 an overpower condition on the input supply was detected by the power monitor. status_mfr_specific code: 0x80, read byte. value after reset: 0x00. table 24. bit descriptions for status_mfr_specific command bits bit name behavior settings description [7] fet_health_bad latched 0 fet behavior appears to be as expected. 1 fet behavior suggests that the fet may be shorted. [6] uv_cmp_out live 0 input voltage to uv pin is above threshold. 1 input voltage to uv pin is below threshold. [5] ov_cmp_out live 0 input voltage to ov pin is below threshold. 1 input voltage to ov pin is above threshold. [4] reserved 0 always reads as 0. [3] hs_inlim latched 0 the adm1276 has not ac tively limited the current into the load. 1 the adm1276 has actively limited current into the load. this bit differs from the iout_oc_fault bit in that the hs_inlim bit is set immediately, whereas the iout_oc_fault bit is not set unless the time limit set by the capacitor on the timer pin elapses. [2:1] hs_shutdown_cause latched 00 the adm1276 is either enabled and working correctly, or has been shut down using the operation command. 01 an iout_oc_fault condition occurred that caused the adm1276 to shut down. 10 a vin_uv_fault condition occurred that caused the adm1276 to shut down. 11 a vin_ov_fault condition occurred that caused the adm1276 to shut down. [0] iout_warn2 latched 0 no overcurrent condition on the output supply detected by the power monitor using the iout_warn2_limit command. 1 an undercurrent or overcurrent co ndition on the output supply was detected by the power monitor using the iout_warn2_limit command. the polarity of the threshold condition is set by the iout_warn2_select bit using the device_config command.
adm1276 rev. 0 | page 40 of 48 read_ein code: 0x86, block read. value after reset: 0x06, 0x0000, 0x00, 0x000000. table 25. byte descriptions for read_ein command byte byte name value description [0] byte count 0x06 always reads as 0x06, the number of data bytes that the block read command should expect to read. [2:1] energy count 0x0000 energy accumulator value in direct format. byte 2 is the high byte, and byte 1 is the low byte. internally, the energy accumulato r is a 24-bit value, but only the most significant 16 bits are returned with this command. use the read_ein_ext command to access the nontruncated version. [3] rollover count 0x00 number of times that the energy count has rolled over from 0x7fff to 0x0000. this is a straight 8-bit binary value. [6:4] sample count 0x000000 this is the total number of pin samples acquired and accumulated in the energy count accumulator. byte 6 is the high byte, byte 5 is the middle byte, and byte 4 is the low byte. this is a straight 24-bit binary value. read_vin code: 0x88, read word. value after reset: 0x0000. table 26. bit descriptions for read_vin command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vin input voltage from the sense+ pin measurement, expressed in adc codes. read_vout code: 0x8b, read word. value after reset: 0x0000. table 27. bit descriptions for read_vout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] vout output voltage from the vout pin measurement, expressed in adc codes. read_iout code: 0x8c, read word. value after reset: 0x0000. table 28. bit descriptions for read_iout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] iout output current from the measurement through the sense resistor, expressed in adc codes. read_pin code: 0x97, read word. value after reset: 0x0000. table 29. bit descriptions for read_pin command bits bit name settings description [15] reserved 0 always reads as 0. [14:0] pin input power from the vin iout calculation. pmbus_revision code: 0x98, read byte. value after reset: 0x22. table 30. bit descriptions for pmbus_revision command bits bit name settings description [7:4] part i revision 0010 always reads as 0010, pmbus specification part i, revision 1.2. [3:0] part ii revision 0010 always reads as 0010, pmbus specification part ii, revision 1.2.
adm1276 rev. 0 | page 41 of 48 mfr_id code: 0x99, block read. value after reset: 0x03 + ascii adi. table 31. byte descriptions for mfr_id command byte byte name value description [0] byte count 0x03 always reads as 0x03, the number of data bytes that the block read command expects to read. [1] character 1 0x41 or a always reads as 0x41. [2] character 2 0x44 or d always reads as 0x44. [3] character 3 0x49 or i always reads as 0x49. mfr_model code: 0x9a, block read. value after reset: 0x09 + ascii adm1276-3. table 32. byte descriptions for mfr_model command byte byte name value description [0] byte count 0x09 always reads as 0x09, the number of data bytes that the block read command expects to read. [1] character 1 0x41 or a always reads as 0x41. [2] character 2 0x44 or d always reads as 0x44. [3] character 3 0x4d or m always reads as 0x4d. [4] character 4 0x31 or 1 always reads as 0x31. [5] character 5 0x32 or 2 always reads as 0x32. [6] character 6 0x37 or 7 always reads as 0x37. [7] character 7 0x36 or 6 always reads as 0x36. [8] character 8 0x2d or C always reads as 0x2d. [9] character 9 0x33 or 3 always reads as 0x33. mfr_revision code: 0x9b, block read. value after reset: 0x01 + ascii 0. table 33. byte descriptions for mfr_revision command byte byte name value description [0] byte count 0x01 always reads as 0x01, the number of data bytes that the block read command expects to read. [1] character 1 0x30 or 0 always reads as 0x30, revision 0 of the adm1276. peak_iout code: 0xd0, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 34. bit descriptions for peak_iout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_iout returns the peak iout curr ent since the register was last cleared. peak_vin code: 0xd1, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 35. bit descriptions for peak_vin command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_vin returns the peak vin volt age since the register was last cleared.
adm1276 rev. 0 | page 42 of 48 peak_vout code: 0xd2, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 36. bit descriptions for peak_vout command bits bit name settings description [15:12] reserved 0000 always reads as 0000. [11:0] peak_vout returns the peak vout voltage since the register was last cleared. pmon_control code: 0xd3, read/write byte. value after reset: 0x01. table 37. bit descriptions for pmon_control command bits bit name settings description [7:1] reserved 0000000 always reads as 0000000. [0] convert 0 power monitor is not running. 1 default. start the sampling of current and volt age with the power monitor. in single shot mode, this bit clears itself after one complete cycle. in continuous mode, this bit must be written to 0 to stop sampling. pmon_config code: 0xd4, read/write byte. value after reset: 0xaf. modifying the power monitor settings while the power monitor is sampling is not supported. the power monitor must be stopped be fore any setting in table 38 is changed to ensure correct operation and to prevent the generation of any potential spurious data and status alerts. table 38. bit descriptions for pmon_config command bits bit name settings description [7] pmon_mode 0 this setting selects single shot sampling mode. 1 default. this setting selects continuous sampling mode. [6] vout_select 0 default. the power monitor sample s the input voltage on the sense+ pin and iout. 1 the power monitor samples the input volt age on the sense+ pin, iout, and the voltage on the vout pin. [5] vrange 0 sets the voltage input range fr om 0 v to 6 v (low input voltage range). 1 default. sets the voltage input range from 0 v to 20 v (high input voltage range). [4] reserved 0 reserved. this bit must always be written as 0. [3] reserved 1 default. this bit must be set to 1 for the power monitor current sense to operate correctly. [2:0] averaging 000 disables sample averaging for current and voltage. 001 sets sample averaging for current and voltage to two samples. 010 sets sample averaging for current and voltage to four samples. 011 sets sample averaging for current and voltage to eight samples. 100 sets sample averaging for current and voltage to 16 samples. 101 sets sample averaging for current and voltage to 32 samples. 110 sets sample averaging for current and voltage to 64 samples. 111 default. sets sample averaging for current and voltage to 128 samples.
adm1276 rev. 0 | page 43 of 48 alert2_config code: 0xd6, read/write word. value after reset: 0x8000. table 39. bit descriptions for alert2_config command bits bit name settings description [15] fet_health_bad_en2 0 disables generation of an smbalert when the fet_health_bad bit is set. 1 default. generates smbalert when the fet_hea lth_bad bit is set. this bit is active from power-up for a fet problem to be de tected and flagged immediately without the need for software to set this bit. [14] iout_oc_fault_en2 0 default. disables generation of an smbalert when the iout_oc_fault bit is set. 1 generates an smbalert when the iout_oc_fault bit is set. [13] vin_ov_fault_en2 0 default. di sables generation of an smbalert when the vin_ov_fault bit is set. 1 generates an smbalert when the vin_ov_fault bit is set. [12] vin_uv_fault_en2 0 default. disables generation of an smbalert when the vin_uv_fault bit is set. 1 generates an smbalert when the vin_uv_fault bit is set. [11] cml_error_en2 0 default. disa bles generation of an smbalert when the cml_error bit is set. 1 generates an smbalert when the cml_error bit is set. [10] iout_oc_warn_en2 0 default. disa bles generation of an smbalert when the iout_oc_warn bit is set. 1 generates an smbalert when the iout_oc_warn bit is set. [9] iout_warn2_en2 0 default. disa bles generation of an smbalert when the iout_warn2 bit is set. 1 generates an smbalert when the iout_warn2 bit is set. [8] vin_ov_warn_en2 0 default. disa bles generation of an smbalert when the vin_ov_warn bit is set. 1 generates an smbalert when the vin_ov_warn bit is set. [7] vin_uv_warn_en2 0 default. disa bles generation of an smbalert when the vin_uv_warn bit is set. 1 generates an smbalert when the vin_uv_warn bit is set. [6] vout_ov_warn_en2 0 default. disa bles generation of an smbalert when the vout_ov_warn bit is set. 1 generates an smbalert when the vout_ov_warn bit is set. [5] vout_uv_warn_en2 0 default. disa bles generation of an smbalert when the vout_uv_warn bit is set. 1 generates an smbalert when the vout_uv_warn bit is set. [4] hs_inlim_en2 0 default. disabl es generation of an smbalert when the hs_inlim bit is set. 1 generates an smbalert when the hs_inlim bit is set. [3] pin_op_warn_en2 0 default. disa bles generation of an smbalert when the pin_op_warn bit is set. 1 generates an smbalert when the pin_op_warn bit is set. [2:1] gpo2_mode 00 default. gpo2 is configured to generate smbalerts. 01 gpo2 can be used as a general-purpose digital output pin. the gpo2_invert bit is used to change the output state. 10 reserved. 11 gpo2 is configured for digital comparator mode. the output pin continuously shows for the selected warning(s) if the relevant warning threshold has been exceeded. in effect, this is an unlatched smbalert. if mult iple bits are selected, the output values are ored together. only warning threshold comparisons affect the pin in this mode. if other bits such as vin_uv_fault_en2 are set, they are ignored in this mode of operation. [0] gpo2_invert 0 default. the gpo2 pin is active low. 1 gpo2 is active high.
adm1276 rev. 0 | page 44 of 48 device_config code: 0xd8, read/write byte. value after reset: 0x00. table 40. bit descriptions for device_config command bits bit name settings description [7] oc_glitch_time 0 default. the long duration glitch filter is used when a severe overcurrent fault is detected. 1 the short duration glitch filter is used when a severe overcurrent fault is detected. [6] flb_disable 0 default. foldback is enabled and can affect the hot swap current sense limit. 1 foldback is disabled and does not affect th e hot swap current sense limit. this setting can be useful if the sole purpose of the flb pin is to act as a power-good input. [5] operation_cmd_en 0 default. the operation command is di sabled, and the adm1276 issues a no acknowledge if the command is received. this setting provides some protection against a card accidentally turning itself off. 1 the operation command is enable d, and the adm1276 responds to it. [4] iout_warn2_select 0 default. configures iout _warn2_limit as an undercurrent threshold. 1 configures iout_warn2_limit as an overcurrent threshold. [3:0] reserved 0000 always reads as 0000. power_cycle code: 0xd9, send byte, no data. peak_pin code: 0xda, read/write word. value after reset: 0x0000 (writing 0x0000 clears the peak value). table 41. bit descriptions for peak_pin command bits bit name settings description [15] reserved 0 always reads as 0. [14:0] peak_pin returns the peak input po wer since the register was last cleared. read_pin_ext code: 0xdb, block read. value after reset: 0x03, 0x000000. table 42. byte descriptions for read_pin_ext command byte byte name value description [0] byte count 0x03 always reads as 0x03, the number of data bytes that the block read command expects to read. [3:1] pin extended 0x000000 result of the vin iout calculation that ha s not been truncated. byte 3 is the high byte, byte 2 is the middle byte, and byte 1 is the low byte. read_ein_ext code: 0xdc, block read. value after reset: 0x08, 0x000000, 0x0000, 0x000000. table 43. byte descriptions for read_ein_ext command byte byte name value description [0] byte count 0x08 always reads as 0x08, the number of data bytes that the block read command expects to read. [3:1] energy count extended 0x000000 24-bit energy accumulator in direct format. byte 3 is the high byte, byte 2 is the middle byte, and byte 1 is the low byte. [5:4] rollover count extended 0x0000 number of times that the energy counter has rolled over from 0x7fff to 0x0000. this is a straight 16-bit binary value. byte 5 is the high byte, and byte 4 is the low byte. [8:6] sample count 0x000000 total number of pin samples acquired and accumulated in the energy count accumulator. byte 8 is the high byte, byte 7 is the middle byte, and byte 6 is the low byte.
adm1276 rev. 0 | page 45 of 48 outline dimensions compliant to jedec standards mo-220-whhc. 111908-a 0.65 bsc 0.70 0.60 0.40 0.35 0.28 0.23 bottom view top view exposed pad p i n 1 i n d i c a t o r 5.10 5.00 sq 4.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 61. 20-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-20-9) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adm1276-3acpz ?40c to +85c 20-lead lfcsp_wq cp-20-9 ADM1276-3ACPZ-RL ?40c to +85c 20-lead lfcsp_wq cp-20-9 1 z = rohs compliant part.
adm1276 rev. 0 | page 46 of 48 notes
adm1276 rev. 0 | page 47 of 48 notes
adm1276 rev. 0 | page 48 of 48 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09718-0-3/11(0)

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